论文信息 - A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs - 字舞流文

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs

V. Kamakoti | Vikram Chandrasekhar | Vivek Garg | Milagros Sashikánth | V. Kamakoti | V. Chandrasekhar | V. Garg | M. Sashikánth