Implementing Abstract Data Structures in Hardware

Despite of the many models of higly parallel computers, the classical yon Neumann architecture will still dominate in the near future for general purpose computing. It is common practice to accelerate sequential computers by replacing software by fast hardware devices like arithmetic co-processors. But there is a growing number of standard problems that can be solved by a special hardware much more efficiently. In this paper we consider the case of abstract data structures. This concept provides the user with a set of procedures for manipulating the data but hides implementation details. In order to apply this concept for designing special hardware, we also have to redesign the data structures involved. We demonstrate this approach f o r heaps supporting Znser£, M~n, DeZMKn, and DeZete operations. Typically, an intermixed sequence of N such operations costs ©CN.log ND sequential time. We show, how to implement heaps on a model of very moderate parallel computation, namely a PRAM with ©Clog N) processors and ~Clog ND global memory without read or write conflicts. This implementation runs in ~CN9 timej e.g. the speed-up is optimal. Previously, heaps supporting Push CfnserZ9 and Pop CDeZMZn9 operations have been studied in [MeSi]. Another important data structures are search trees. Parallel insertions resp. deletions in a-3 trees are studied in [PVW].