A robust method to estimate Power and Delay for Digital Integrated Circuits

Advancements in nano-scale Integrated Circuits manufacturing technology has resulted in variability of performance metrics. The performance parameters such as Power and Delay are no longer represented deterministically. As a result, circuit designers and manufacturers need to make use of statistical analysis to estimate performance of Integrated Circuits. In this paper we present a new methodology to increase the accuracy of estimation compared to prior methods. We introduce Bayesian analysis as a powerful mathematical and statistical approach to incorporate the prior observations in calculating the Probability Density Function (PDF) of performance parameters like Power and Delay. We apply this technique on a few Digital Gates and compare the results with previous methods. We also introduce Bayesian analysis as a powerful method to update the PDF of performance parameters. Finally, we demonstrate how this statistical approach could supersede the approaches established on Frequentist analysis so as to achieve a more accurate estimation on Power and Delay for Digital Integrated Circuits.