10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times

This 4-TBPS packet switch uses a combined input- and crosspoint-queued (CICQ) structure with virtual output queuing at the ingress to achieve the scalability of input-buffered switches, the performance of output-buffered switches, and low latency.

[1]  C. Minkenberg,et al.  A combined input and output queued packet switched system based on PRIZMA switch on a chip technology , 2000, IEEE Communications Magazine.

[2]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[3]  Masayoshi Nabeshima Performance Evaluation of a Combined Input- and Crosspoint-Queued Switch , 2000 .

[4]  Nick McKeown,et al.  Matching output queueing with a combined input/output-queued switch , 1999, IEEE J. Sel. Areas Commun..

[5]  Cyriel Minkenberg,et al.  Current issues in packet switch design , 2003, CCRV.

[6]  Eiji Oki,et al.  CIXOB-k: combined input-crosspoint-output buffered packet switch , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[7]  F. M. Chiussi,et al.  Low-cost scalable switching solutions for broadband networking: the ATLANTA architecture and chipset , 1997 .

[8]  Hui Zhang,et al.  Implementing distributed packet fair queueing in a scalable switch architecture , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[9]  Dimitrios N. Serpanos,et al.  Switching fabrics with internal backpressure using the ATLAS I single-chip ATM switch , 1997, GLOBECOM 97. IEEE Global Telecommunications Conference. Conference Record.

[10]  Nicolas D. Georganas,et al.  16*16 limited intermediate buffer switch module for ATM networks , 1991, IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record.

[11]  Naoaki Yamanaka,et al.  High-speed ATM switch with input and cross-point buffers , 1993 .

[12]  Cyriel Minkenberg,et al.  Optimized architecture and design of an output-queued CMOS switch chip , 2001, Proceedings Tenth International Conference on Computer Communications and Networks (Cat. No.01EX495).

[13]  Tara Javidi,et al.  A high-throughput scheduling algorithm for a buffered crossbar switch fabric , 2001, ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240).

[14]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[15]  Anna Charny,et al.  On the speedup required for work-conserving crossbar switches , 1999, IEEE J. Sel. Areas Commun..