Porous dielectric dual damascene patterning issues for 65 nm node: can architecture bring a solution?
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O. Louveau | H. Feldis | M. Assous | D. Louis | M. Fayolle | Joaquim Torres | A. Roman | E. Tabouret | J. Simon | Lucile Broussous | C. Bourlot
[1] P. Besson,et al. Post SiN Etching Cleaning During Copper and Low K Integration , 2001 .