Coordinating processor and main memory for efficientserver power control
暂无分享,去创建一个
Xue Li | Xiaorui Wang | Ming Chen | Xiaorui Wang | Xue Li | Ming Chen
[1] Bruce Jacob,et al. Memory Systems: Cache, DRAM, Disk , 2007 .
[2] Zhao Zhang,et al. Thermal modeling and management of DRAM memory systems , 2007, ISCA '07.
[3] Jan M. Maciejowski,et al. Predictive control : with constraints , 2002 .
[4] Xiaorui Wang,et al. MIMO Power Control for High-Density Servers in an Enclosure , 2010, IEEE Transactions on Parallel and Distributed Systems.
[5] Karthick Rajamani,et al. A performance-conserving approach for reducing peak power consumption in server systems , 2005, ICS '05.
[6] Zhao Zhang,et al. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[7] Margaret Martonosi,et al. Formal online methods for voltage/frequency control in multiple clock domain microprocessors , 2004, ASPLOS XI.
[8] Xiaodong Li,et al. Performance directed energy management for main memory and disks , 2004, ASPLOS XI.
[9] Gargi Dasgupta,et al. Server Workload Analysis for Power Minimization using Consolidation , 2009, USENIX Annual Technical Conference.
[10] Margaret Martonosi,et al. Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[11] Wolf-Dietrich Weber,et al. Power provisioning for a warehouse-sized computer , 2007, ISCA '07.
[12] Aamer Jaleel,et al. DRAMsim: a memory system simulator , 2005, CARN.
[13] Kevin Skadron,et al. Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.
[14] Xiaorui Wang,et al. Power capping: a prelude to power shifting , 2008, Cluster Computing.
[15] Li Shang,et al. PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] B. Anderson,et al. Digital control of dynamic systems , 1981, IEEE Transactions on Acoustics, Speech, and Signal Processing.
[17] AbdelzaherTarek,et al. Dynamic Voltage Scaling in Multitier Web Servers with End-to-End Delay Control , 2007 .
[18] Xiaodong Li,et al. Cross-component energy management: Joint adaptation of processor and memory , 2007, TACO.
[19] Margaret Martonosi,et al. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[20] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[21] Ricardo Bianchini,et al. Limiting the power consumption of main memory , 2007, ISCA '07.
[22] Zhao Zhang,et al. Software thermal management of dram memory for multicore systems , 2008, SIGMETRICS '08.
[23] Kai Ma,et al. Scalable power control for many-core architectures running multi-threaded applications , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[24] Xiaorui Wang,et al. SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.
[25] Karthick Rajamani,et al. Energy Management for Commercial Servers , 2003, Computer.
[26] Tor Arne Johansen,et al. Hardware Synthesis of Explicit Model Predictive Controllers , 2007, IEEE Transactions on Control Systems Technology.
[27] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.
[28] Vanish Talwar,et al. No "power" struggles: coordinated multi-level power management for the data center , 2008, ASPLOS.
[29] Kai Ma,et al. Temperature-constrained power control for chip multiprocessors with online model estimation , 2009, ISCA '09.
[30] Aamer Jaleel,et al. Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.