Efficient A it Synthesis with ~~~~ltan~o~s Yie

This paper presents an eficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The starting point of this methodology is a declarative analytical description of the circuit. An equation manipulation program based on constraint satisfaction converts this declarative model into an efJicient design plan for optimization based sizing. The eficiency is due to the use of an operating point driven DC formulation, so that the design plan avoids the calculation ojsimultaneous sets of nonlinear equations. From the same declarative analytical description also a direct symbolic yield estimation plan is generated. The parametric yield is estimated by propagating the spread of the technological variables through the analytical model towards the performance variables of the circuit. The design plan and the yield estimation plan aye then combined together in the inner loop of a global optimization routine. The strength of this methodology lies in the low CPU times needed to perform yield estimation compared to the hours of simulation batches with Monte Carlo simulations, while the accuracy is comparable. Designing an analog circuit is one thing, producing it is another. Real-life technology parameter variations make the circuits fail for some or all of the specifications if no precautions are taken. The ratio of the number of successful circuits over the number of produced circuits is the total yield. The total yield consists of yield due to production faults and yield due to soft faults. In this paper we concentrate on the yield based on the soft faults, generated by the technology parameter variations: the parametric yield.