Memristor based memories: Technology, design and test

Today's memory technologies, such as DRAM, SRAM, and NAND Flash, are facing major challenges with regard to their continued scaling. For instance, ITRS projects that DRAM cannot scale easily below 40nm as the cost and energy/power are hard -if not impossible- to scale. Fortunately, the international memory technology community has been researching other alternative for more than fifteen years. Apparently, non-volatile resistive memories are promising to replace the today's memories for many reasons such as better scalability, low cost, higher capacity, lower energy, CMOS compatibility, better configurability, etc. This paper discusses and highlights three major aspects of resistive memories, especially memristor based memories: (a) technology and design constraints, (b) architectures, and (c) testing and design-for-test. It shows the opportunities and the challenges.

[1]  Said Hamdioui,et al.  Memory Fault Modeling Trends: A Case Study , 2004, J. Electron. Test..

[2]  Sachhidh Kannan,et al.  Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories , 2013, IEEE Transactions on Nanotechnology.

[3]  Yong-Bin Kim,et al.  A novel “divide and conquer” testing technique for memristor based lookup table , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[4]  R. Waser,et al.  Thermochemical resistive switching: materials, mechanisms, and scaling projections , 2011 .

[5]  Kailash Gopalakrishnan,et al.  Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..

[6]  Stefan K. Lai,et al.  Flash memories: Successes and challenges , 2008, IBM J. Res. Dev..

[7]  T. Cabout,et al.  Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories , 2014, IEEE Transactions on Electron Devices.

[8]  Lifeng Liu,et al.  A Simplified Model for Resistive Switching of Oxide-Based Resistive Random Access Memory Devices , 2012, IEEE Electron Device Letters.

[9]  L. Chua Memristor-The missing circuit element , 1971 .

[10]  Georgios Ch. Sirakoulis,et al.  Improved read voltage margins with alternative topologies for memristor-based crossbar memories , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[11]  W. E. Beadle,et al.  Switching properties of thin Nio films , 1964 .

[12]  Sachhidh Kannan,et al.  Sneak-path Testing of Memristor-based Memories , 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

[13]  R. Dittmann,et al.  Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges , 2009, Advanced materials.

[14]  Jean Michel Portal,et al.  A novel test structure for OxRRAM process variability evaluation , 2013, Microelectron. Reliab..

[15]  Said Hamdioui,et al.  Memory test experiment: industrial results and data , 2006 .

[16]  S. Balatti,et al.  Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM—Part I: Experimental Study , 2012, IEEE Transactions on Electron Devices.

[17]  Said Hamdioui,et al.  On Defect Oriented Testing for Hybrid CMOS/Memristor Memory , 2011, 2011 Asian Test Symposium.

[18]  Khaled N. Salama,et al.  Memristor-based memory: The sneak paths problem and solutions , 2013, Microelectron. J..

[19]  R. Waser,et al.  A Novel Reference Scheme for Reading Passive Resistive Crossbar Memories , 2006, IEEE Transactions on Nanotechnology.

[20]  Said Hamdioui,et al.  New data-background sequences and their industrial evaluation for word-oriented random-access memories , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Kyeong-Sik Min,et al.  Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array , 2012, IEEE Transactions on Nanotechnology.

[22]  Georgios Ch. Sirakoulis,et al.  Nano-Crossbar Memories Comprising Parallel/Serial Complementary Memristive Switches , 2014 .

[23]  D. Strukov,et al.  Prospects for terabit-scale nanoelectronic memories , 2004 .

[24]  Said Hamdioui,et al.  Testing Open Defects in Memristor-Based Memories , 2015, IEEE Transactions on Computers.

[25]  Nirmal Ramaswamy Invited) Challenges in Engineering RRAM technology for high density applications , 2012 .

[26]  Sachhidh Kannan,et al.  Detection, diagnosis, and repair of faults in memristor-based memories , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[27]  Seungjun Kim,et al.  Flexible memristive memory array on plastic substrates. , 2011, Nano letters.

[28]  Arnaud Virazel,et al.  Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[29]  Byung Joon Choi,et al.  Engineering nonlinearity into memristors for passive crossbar applications , 2012 .

[30]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[31]  Said Hamdioui,et al.  DfT schemes for resistive open defects in RRAMs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[32]  An Chen,et al.  Electronic Effect Resistive Switching Memories , 2014 .

[33]  Sachhidh Kannan,et al.  Sneak path testing and fault modeling for multilevel memristor-based memories , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

[34]  An Chen,et al.  Variability of resistive switching memories and its impact on crossbar array performance , 2011, 2011 International Reliability Physics Symposium.

[35]  Lin Chen,et al.  Device and SPICE modeling of RRAM devices. , 2011, Nanoscale.

[36]  Wei Yi,et al.  AC sense technique for memristor crossbar , 2012 .

[37]  Wei Wang,et al.  Design considerations for variation tolerant multilevel CMOS/Nano memristor memory , 2010, GLSVLSI '10.

[38]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[39]  J. W. McPherson Reliability Trends with Advanced CMOS Scaling and The Implications for Design , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[40]  S. Balatti,et al.  Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM—Part II: Modeling , 2012, IEEE Transactions on Electron Devices.

[41]  T.G. Noll,et al.  Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[42]  Cong Xu,et al.  Design trade-offs for high density cross-point resistive memory , 2012, ISLPED '12.

[43]  M. Kozicki,et al.  Electrochemical metallization memories—fundamentals, applications, prospects , 2011, Nanotechnology.