SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation
暂无分享,去创建一个
[1] Robert B. Jones,et al. Abstraction by Symbolic Indexing Transformations , 2002, FMCAD.
[2] Chao Wang,et al. Abstraction refinement in symbolic model checking using satisfiability as the only decision procedure , 2005, International Journal on Software Tools for Technology Transfer.
[3] Niklas Sörensson,et al. An Extensible SAT-solver , 2003, SAT.
[4] Per Bjesse,et al. Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers , 2001, CAV.
[5] Magdy S. Abadir,et al. Formal verification of content addressable memories using symbolic trajectory evaluation , 1997, DAC.
[6] Koen Claessen,et al. A New SAT-Based Algorithm for Symbolic Trajectory Evaluation , 2005, CHARME.
[7] Randal E. Bryant,et al. Formal verification by symbolic evaluation of partially-ordered trajectories , 1995, Formal Methods Syst. Des..
[8] Orna Grumberg,et al. Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation , 2006, CAV.
[9] George J. Milne,et al. Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.
[10] Thomas Schubert,et al. High-level formal verification of next-generation microprocessors , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[11] G. G. Stokes. "J." , 1890, The New Yale Book of Quotations.
[12] Koen Claessen,et al. Explaining Symbolic Trajectory Evaluation by Giving It a Faithful Semantics , 2006, CSR.
[13] Carl-Johan H. Seger,et al. A Methodology for Large-Scale Hardware Verification , 2000, FMCAD.