Modeling and Testing Process Variation in Nanometer CMOS

As device technology progresses toward 45nm and beyond, the fidelity of the process parameter modeling becomes questionable. In this paper we propose the concept of process variation (PV) testing. This is achieved by applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, our architecture looks at the effect of PV in a chip indirectly and collectively. The novelty of this architecture is in shifting the strategy of VLSI testing to frequency domain by using a distributed network of frequency-sensitive circuits such as ring oscillators. This provides an intrinsic advantage by minimizing the effect of noise (signal integrity loss, crosstalk, IR drop, etc.) and by using the powerful concept of digital signal processing for test analysis. The test architecture does not interfere with the rest of the circuit thus providing freedom to tune accuracy of the PV test by choosing the proper number and type of oscillators

[1]  S. Nassif,et al.  Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[2]  Vivek De,et al.  Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..

[3]  C.H. Kim,et al.  An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations , 2004, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[4]  James D. Meindl,et al.  Impact of within-die parameter fluctuations on future maximum clock frequency distributions , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[5]  Yuhua Cheng,et al.  The influence and modeling of process variation and device mismatch for analog/rf circuit design , 2002, Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611).

[6]  Dhruva Acharyya,et al.  Hardware results demonstrating defect detection using power supply signal measurements , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[7]  P. Zarkesh-Ha,et al.  Characterization and modeling of clock skew with process variations , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[8]  Cameron Dryden.  Survey of design and process failure modes for high-speed SerDes in nanometer CMOS , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[9]  Costas J. Spanos,et al.  RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION , 1996 .

[10]  Sani R. Nassif.  Design for Variability in DSM Technologies , 2000 .

[11]  H. Masuda,et al.  Accurate statistical process variation analysis for 0.25-/spl mu/m CMOS with advanced TCAD methodology , 1998 .

[12]  Chandu Visweswariah,et al.  Death, taxes and failing chips , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[13]  Kaushik Roy,et al.  Leakage and process variation effects in current testing on future CMOS circuits , 2002, IEEE Design & Test of Computers.

[14]  M. Berroth,et al.  CMOS ring oscillator with quadrature outputs and 100 MHz to 3.5 GHz tuning range , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[15]  W. Edwards Deming,et al.  Some Theory of Sampling , 1950 .

[16]  W. Edwards Deming.  Some theory of sampling , 1951 .

[17]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[18]  Ali Keshavarzi,et al.  Parametric failures in CMOS ICs - a defect-based analysis , 2002, Proceedings. International Test Conference.

[19]  R. Otten,et al.  Statistical timing for parametric yield prediction of digital integrated circuits , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[20]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[21]  Ramesh Harjani,et al.  A low-phase-noise CMOS ring oscillator with differential control and quadrature outputs , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[22]  Shekhar Y. Borkar,et al.  Microarchitecture and Design Challenges for Gigascale Integration , 2004, MICRO.

[23]  Andrea Neviani,et al.  Analysis of the impact of process variations on clock skew , 2000 .

[24]  Weiping Shi,et al.  Longest-path selection for delay test under process variation , 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Keith Baker,et al.  Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[26]  C. S. Murthy,et al.  Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs] , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..