Simulation and Measurement of an On-Die Power-Gated Power Delivery System

For low-power design, power switch gate is introduc ed to the SOC to reduce the leakage current from the un-used IP block during power-savi ng mode. However, it introduces additional IR loss and reduces the voltage margin. It also induces huge current spike and pulls down the on-package voltage to almost zero du ring the switch gate turn-on transition to charge up the on-die decap. This pape r demonstrates the full-path simulation and lab measurement to characterize the gated PDN behav ior. Mitigation solution for the tight DC margin and on-package sudden voltage droop is rovided. Good correlation between silicon and measurement is shown.