Capacitive Inter-Chip Data and Power Transfer for 3-D VLSI

We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mum silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1Hz-15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration

[1]  Eugenio Culurciello,et al.  Monolithic digital galvanic isolation buffer fabricated in silicon on sapphire CMOS , 2005 .

[2]  R. Berger,et al.  Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[3]  Ya-Hong Xie,et al.  High-performance on-chip transformers , 2005 .

[4]  N. Miura,et al.  A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS) , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[5]  K. W. Lee,et al.  Three-dimensional shared memory fabricated using wafer stacking technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[6]  Eugenio Culurciello,et al.  Isolation charge pump fabricated in silicon on sapphire CMOS technology , 2005 .

[7]  Ki-Tae Park,et al.  Neuromorphic vision chip fabricated using three-dimensional integration technology , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[8]  Jongsun Kim,et al.  A low power capacitive coupled bus interface based on pulsed signaling , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[9]  S. K. Kim,et al.  Three-dimensional integration: technology, use, and issues for mixed-signal applications , 2003 .

[10]  Mitsumasa Koyanagi,et al.  Future system-on-silicon LSI chips , 1998, IEEE Micro.

[11]  D.D. Antono,et al.  1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  Jeffrey Hopwood,et al.  An SOI-based three-dimensional integrated circuit technology , 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

[13]  John F. Dickson,et al.  On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique , 1976 .

[14]  T. Nakamura,et al.  Intelligent image sensor chip with three dimensional structure , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[15]  R. Ho,et al.  Proximity communication , 2004, IEEE Journal of Solid-State Circuits.

[16]  Alyssa B. Apsel,et al.  Silicon on sapphire CMOS for optoelectronic microsystems , 2001 .

[17]  Paul D. Franzon,et al.  4 Gbps high-density AC coupled interconnection , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[18]  J. Patel,et al.  Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs) , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[19]  P. Franzon,et al.  Buried bump and AC coupled interconnection technology , 2004, IEEE Transactions on Advanced Packaging.

[20]  K. Haberger,et al.  Process technology for 3D-CMOS devices , 1989, IEEE SOS/SOI Technology Conference.