A novel low power and high speed Multiply-accumulate (MAC) unit design for floating-point numbers

At the present days, the low power designs are playing a vital role in every designs. Due to the existence of the battery designs in the integrated circuits the low power designs play a major role of operations in any circuit. In this paper our work is on a low power and high speed Multiply-accumulate unit that is the basic block in digital processing systems. Since, the basic blocks of MAC unit are multiplier, adder and accumulator. The design of these blocks should be efficient in terms of the power and speed. So our work is based on the BCD multiplication and addition and also to find the floating point numbers. Our implementation consists of multiplier, register, binary to BCD converter; Adder and BCD block which make the overall output of the MAC to be in the BCD format. First the individual blocks are designed and analyzed and the overall MAC is implemented in Cadence 0.9μm technology and power and delay analysis is done using the cadence spectre.

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