저전력 500㎒ CMOS PLL 주파수합성기 설계

This paper describes a frequency synthesizer designed in a 0.25㎛ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power charaeteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250㎒ to 800㎒ and consumes 1.08㎃ at 500㎒ from a 2.5V supply. The measured phase noise is -85㏈c/㎐ in-band and -105㏈c/㎐ at 1㎒ offset. The die area is 1.09㎟.