The evolution of build-up package technology and its design challenges

This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

[1]  J. R. Millar 263. Interpenetrating polymer networks. Styrene–divinylbenzene copolymers with two and three interpenetrating networks, and their sulphonates , 1960 .

[2]  Tadashi Nakamura,et al.  The progress of the ALIVH substrate , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[3]  Yutaka Tsukada,et al.  Surface laminar circuit packaging , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[4]  J. Joly,et al.  Solutions to the needs for higher interconnect density on PWB's : Build up technology and Micro vias , 1999 .

[5]  John G. Torok,et al.  Packaging the IBM eServer z990 central electronic complex , 2004, IBM J. Res. Dev..

[6]  Rama K. Shukla,et al.  Flip chip CPU package technology at Intel: a technology and manufacturing overview , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

[7]  Mirng-Ji Lii,et al.  Flip chip pin grid array (FC-PGA) packaging technology , 2000, Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456).

[8]  E. Colgan,et al.  A practical implementation of silicon microchannel coolers for high power chips , 2005, Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005..

[9]  M. Shimizu,et al.  Technical trends of LSI packaging: recent advances in CSPs and high density substrates , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[10]  Michael A. Gaynes,et al.  Effects of mechanical stress and moisture on packaging interfaces , 2005, IBM J. Res. Dev..

[11]  M Kato,et al.  High reliability, high density build up printed circuit board for MCM-L. , 1995 .

[12]  Yervant Zorian,et al.  2003 technology roadmap for semiconductors , 2004, Computer.

[13]  Clarissa Navarro Development of a standard test method for evaluating conductive anodic filament (CAF) growth failure in PCBs , 2002 .

[14]  S. Ramalingam,et al.  Challenges of flip chip on organic substrate assembly technology , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

[15]  D.N. de Aranjo,et al.  Substrate design optimization for high speed links , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[16]  Cw Lee,et al.  Micro via filling plating technology for IC substrate applications , 2004 .

[17]  Vasa Kosadat,et al.  Integrated supply chain , 2001 .

[18]  Henning Braunisch,et al.  Electrical performance of bumpless build-up layer packaging , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[19]  D. D. Araujo,et al.  Substrate Design Optimization for High Speed Links , 2003 .

[20]  D. Wood,et al.  Pentium 4 processor package design and development , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[21]  I. Ho An ovenview of SBU (Sequential Build-Up)/Microvia technologies? , 1997, Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces.

[22]  Alan G. Klopfenstein Microelectronics Packaging Handbook , 1997, Springer US.