Way-variable Caches for Static Power Reduction
暂无分享,去创建一个
[1] Vivek De,et al. A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[2] David Blaauw,et al. Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.
[3] Gary S. Tyson,et al. Eager writeback-a technique for improving bandwidth utilization , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[4] David H. Albonesi,et al. Selective cache ways: on-demand cache resource allocation , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.
[5] Mircea R. Stan,et al. Circuit-level techniques to control gate leakage for sub-100nm CMOS , 2002, ISLPED '02.
[6] Kaushik Roy,et al. Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.
[7] Margaret Martonosi,et al. Let caches decay: reducing leakage energy via exploitation of cache generational behavior , 2002, TOCS.
[8] Norman P. Jouppi,et al. CACTI 2.0: An Integrated Cache Timing and Power Model , 2002 .