Way-variable Caches for Static Power Reduction

Power consumption due to leakage increases rapidly as devices scale to smaller geometries. We propose way-variable caches that dynamically adapt the number of active ways according to runtime requirements. By entirely gating the unused ways from the voltage supply, the leakage can be significantly reduced. We then apply an original algorithm utilizing data access locality to make proper resizing decisions. Performance evaluations are done with a superscalar processor model having 16-KB, 4-way set-associative L1 instruction and data caches. The results verified that, on average, 1.7 ways of the instruction cache can be disabled with only 1.3% performance degradation in the case of instruction cache. The values are 1.5 ways and 1.1% in the case of the data cache.

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