Interconnect width selection for deep submicron designs using the table lookup method

Interconnect width sizing is critical in deep submicron designs to reduce the overall delay. In this paper we present an algorithm for optimal interconnect width selection from a predetermined and precharacterized wire width metric. This algorithm uses a 4-dimensional lookup table approach based on "O'Brien, Savarino" π model for the interconnect load. This methodology can easily be integrated into the existing design tools since this methodology lies in the middle of the postplacement and prerouting step of the physical design flow. We will explore a trade-off between delay and power dissipation for different widths and a comparison will also be made with the ITRS design rules.

[1]  Jason Cong,et al.  Interconnect performance estimation models for design planning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  P. R. O'Brien,et al.  Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, ICCAD 1989.

[3]  Chandramouli V. Kashyap,et al.  An "effective" capacitance based delay metric for RC interconnect , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[4]  Dirk Stroobandt,et al.  The interpretation and application of Rent's rule , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Yu-Min Lee,et al.  Optimal wire-sizing function under the Elmore delay model with bounded wire sizes , 2002 .

[6]  Dirk Stroobandt,et al.  Efficient representation of interconnection length distributions using generating polynomials , 2000, SLIP '00.

[7]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[8]  Dirk Stroobandt,et al.  A Priori Wire Length Estimates for Digital Design , 2001 .

[9]  Jason Cong,et al.  Wire width planning for interconnect performance optimization , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Charles J. Alpert,et al.  Interconnect synthesis without wire tapering , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..