Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers

This paper compares 130nm custom silicon implementations of three scalable Montgomery multiplier architectures to previously published FPGA implementations of the same architectures. It investigates the delay, energy, and area tradeoffs of parallelized left-shifting radix-2, radix-4, and Booth-encoded radix-4 architectures. The radix-4 architecture is most efficient, performing 256 × 256-bit modular multiplication in 453ns while consuming 15.7nJ of energy and occupying an area of 0.141mm2. The radix-2 architecture is a close second, with an energy-delay product (EDP) 0.8% higher and an area-delay product (ADP) 3.1% higher. The Booth-encoded radix-4 architecture eliminates the need for an adder generating a 3× multiple, but comes at a cost of 36% in EDP and 34% in ADP relative to the conventional radix-4 architecture. The relative efficiencies of the silicon implementations are consistent with the FPGA implementations.