Figure 12.1 shows the architecture of the mixed signal IC design of reference [12.10]. The IC is part of the read/write channel of a rigid media disk drive. A 20mV read signal is variably amplified, sampled and equalized under digital control with maximum likelihood sequence detection. An analog AGC (Automatic Gain Control Amplifier), Buffer amplifiers, delay lines, multiple VCOs (Voltage Controlled Oscillator) and PLLs (Phase Locked Loop), D/As and A/D coexist with 6K CMOS gates clocked at 27Mhz. This 5.5mm square chip, packaged in a 68-pin PLCC, uses a 5V, BICMOS process with 1 um Leff and 6 Ghz NPN. The architecture of this IC is explained in reference [12.15]. In Figure 12.1 the amplified signal from the disk surface (A) must be equalized and sampled as shown in waveform (B). Waveform (W) shows the write current waveform that wrote the data of waveform (A) on the disk surface. Figure 12.2 shows a more complex write waveform and the resultant data of waveform (B).
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