Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA

This paper presents a method that permits to estimate the power consumption of components in the AADL component assembly model, once deployed onto components in the AADL target platform model. This estimation is performed at different levels in the AADL refinement process. Multi-level power models have been specifically de- veloped for the different type of possible hardware targets: General Pur- pose Processors (GPP), Digital Signal Processors (DSP) and Field Pro- grammable Gate Arrays (FPGA). Three models are presented for a com- plex DSP (the Texas Instrument C62), a RISC GPP (the PowerPC 405), and a FPGA from Altera (Stratix EP1S80). The accuracy of these models depends on the refinement level. The maximum error introduced ranges from 70% for the FPGA at the first refinement level (only the operating frequency is considered here) to 5% for the GPP at the third refinement level (where the component's actual source code is considered).

[1]  Kees G. W. Goossens,et al.  The Petrol approach to high-level power estimation , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[2]  Eric Senn,et al.  SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications , 2005, EURASIP J. Adv. Signal Process..

[3]  Thomas Vergnaud,et al.  Modélisation des systèmes temps-réel répartis embarqués pour la génération automatique d'applications formellement vérifiées , 2006 .

[4]  Peter Marwedel,et al.  An Accurate and Fine Grain Instruction-Level Energy Model Supporting Software Optimizations , 2007 .

[5]  Peng Yang,et al.  PowerViP: SoC power estimation framework at transaction level , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[6]  Luca Benini,et al.  Cycle-accurate power analysis for multiprocessor systems-on-a-chip , 2004, GLSVLSI '04.

[7]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Steve Vestal,et al.  The SAE Architecture Analysis & Design Language (AADL) a standard for engineering performance critical systems , 2006, 2006 IEEE Conference on Computer Aided Control System Design, 2006 IEEE International Conference on Control Applications, 2006 IEEE International Symposium on Intelligent Control.

[9]  Narayanan Vijaykrishnan,et al.  A power estimation methodology for systemC transaction level models , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[10]  Etienne Borde,et al.  Automatic Composition of AADL Models for the Verification of Critical Component-Based Embedded Systems , 2008, 13th IEEE International Conference on Engineering of Complex Computer Systems (iceccs 2008).

[11]  Jean-Luc Dekeyser,et al.  Estimating Energy Consumption for an MPSoC Architectural Exploration , 2006, ARCS.

[12]  Fabrice Kordon,et al.  Rapid Prototyping of Intrusion Detection Systems , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[13]  Eric Senn,et al.  Power Consumption Modeling and Characterization of the TI C6201 , 2003, IEEE Micro.

[14]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[15]  M. Potkonjak,et al.  Function-level power estimation methodology for microprocessors , 2000, Proceedings 37th Design Automation Conference.

[16]  Eric Senn,et al.  High-level synthesis under I/O timing and memory constraints , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[17]  Laurent Nana,et al.  Scheduling and memory requirements analysis with AADL , 2005 .

[18]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[19]  Jean-Philippe Diguet,et al.  Refining power consumption estimations in the component based AADL design flow , 2008, 2008 Forum on Specification, Verification and Design Languages.

[20]  Eric Senn,et al.  Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design-Flow , 2006 .

[21]  Laurent Pautet,et al.  Rapid Prototyping of Distributed Real-Time Embedded Systems Using the AADL and Ocarina , 2007, IEEE International Workshop on Rapid System Prototyping.

[22]  Eric Senn,et al.  Functional level power analysis: an efficient approach for modeling the power consumption of complex processors , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.