论文信息 - Optimizing Memory Throughput In a Tightly Coupled Multiprocessor

Optimizing Memory Throughput In a Tightly Coupled Multiprocessor

Professional positions sept 1994 present: “directeur de recherches” at IRISA/INRIA, Head of the CAPS team (Compiler and Architecture for Supercalar and embedded Processors) and Systems) since 1994. The CAPS team is a group of 5 senior researchers, 13 Ph.D students and 4 engineers. Feb. 1999Feb. 2000: Sabbatical year from INRIA, spent with VSSAD, Alpha Development Group at Compaq (Shrewsbury, Massuchussets). oct 1986 sept 1994: “chargé de recherches” at IRISA/INRIA (Institut National de Recherches en Informatique et Automatique), in the CALCPAR (Parallel Computer) team sept 1983 oct 1986: research assistant at IRISA/INRIA, supported by a fellowship from CNET (Centre National des Études et Télécommunications)

Yvon Jégou | André Seznec

[1] Yvon Jégou,et al. Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache , 1988, ICS '88.

[2] Yvon Jégou,et al. Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments , 1986, J. Parallel Distributed Comput..

[3] Yvon Jégou,et al. A asynchronous buffering network for tightly coupled multiprocessors , 1989, ICS '89.