Power optimization for pipeline analog-to-digital converters
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Power optimization for pipeline analog-to-digital converters (ADCs) is presented. Pipeline ADCs with identical stages, parallel multiplying digital-to-analog converters (MDACs), capacitor scaling and resolution scaling are considered. Given the ratio R between the power consumption by each MDAC and that by each comparator in the sub-ADCs, the optimum bit resolution/stage and the corresponding minimum total power consumption are derived for each architecture. ADCs with capacitor scaling always achieve the lowest minimum power consumption. For ADCs with identical stages with a typical power ratio R of 10 to 20, the optimum number of bits/stage should be three or even four. These results serve as useful guidelines for designers in choosing the optimum number of bits/stage to minimize the ADC's power consumption.
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