Look-up table FPGA realization of m-out-of-n bit voters

Voting is a fundamental operation in the realization of fault-tolerant hardware modules. Different techniques to design bit voters have been proposed in the past; the most common is based on sparse logic implementation of two/multi-level specifications. Though results for these kinds of implementations are optimal or near to optimal in terms of area and speed of the synthesized circuit, physical realization and testing may require a long time. We present results on the implementation of m-out-of-n bit voters at the FPGA level.<<ETX>>