Process integration technologies for a 0.3 /spl mu/m BiCMOS SRAM with 1.5 V operation

This paper describes the process integration technologies for low voltage BiCMOS SRAM operation, including a low collector resistance process, a high energy ion implanted p-type isolation, a symmetrical cell layout design and an optimized gate oxide thickness for a boost circuit. These technologies were successfully implemented using 0.3 /spl mu/m BiCMOS devices where an address access time of 6 ns was demonstrated at 1.5 V for a 4 Mb BiCMOS SRAM.