PLEST: A Program for Area Estimation of VLSI Integrated Circuits

This paper describes PLEST, a program for estimating the area of standard cell layouts as part of the more general ARREST area estimator embedded in the ADAM system. PLEST is based on a probabilistic model for placement of logic. Given various design parameters, PLEST generates a range of estimates for the possible shapes of the block layout. The program was applied to a set of six layouts. The estimated chip area is, for all six chips, within 10% of the measured area. Further research will be aimed at estimating layout area consumption starting from the register-transfer level design description.

[1]  John J. Granacki,et al.  The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance , 1983, 20th Design Automation Conference Proceedings.

[2]  A. Feller,et al.  A speed oriented fully automatic layout program for random logic VLSI devices , 1978, AFIPS National Computer Conference.

[3]  Ikuo Harada,et al.  CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  D W Knapp,et al.  A Data Structure for VLSI Synthesis and Verification , 1983 .

[5]  John J. Granacki,et al.  The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface , 1985, 22nd ACM/IEEE Design Automation Conference.

[6]  William R. Heller,et al.  Prediction of wiring space requirements for LSI , 1977, DAC '77.

[7]  Alice C. Parker,et al.  A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..