Novel SER standards: Backgrounds and methodologies

Standard methods to quantify SER susceptibility in memory devices have been established during 2000–2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.

[1]  E. Ibe,et al.  Installation and application of an intense 7Li(p,n) neutron source for 20-90 MeV region. , 2007, Radiation protection dosimetry.

[2]  M. Cabanas-Holmen,et al.  Heavy Ion and High Energy Proton-Induced Single Event Transients in 90 nm Inverter, NAND and NOR Gates , 2009, IEEE Transactions on Nuclear Science.

[3]  Nicholas P. Carter,et al.  Cross-layer reliability , 2010 .

[4]  Eishi Ibe.  Scaling Effects on Neutron-Induced Soft Error in SRAMs Down to 22 nm Process S , 2009 .

[5]  A. KleinOsowski,et al.  Clock and Reset Transients in a 90 nm RHBD Single-Core Tilera Processor , 2009, IEEE Transactions on Nuclear Science.

[6]  C. D. Bowman,et al.  The Los Alamos National Laboratory Spallation Neutron Sources , 1990 .

[7]  Takashi S. Nakamura,et al.  Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices , 2008 .

[8]  R. Baumann,et al.  Neutron-induced boron fission as a major source of soft errors in deep submicron SRAM devices , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[9]  Dan Alexandrescu,et al.  A Systematical Method of Quantifying SEU FIT , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[10]  T. Makino,et al.  Soft-Error Rate in a Logic LSI Estimated From SET Pulse-Width Measurements , 2009, IEEE Transactions on Nuclear Science.

[11]  D.L. Hansen,et al.  Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology , 2009, IEEE Transactions on Nuclear Science.

[12]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[13]  Naohiro Hirakawa,et al.  Development of monoenergetic neutron calibration fields between 8 keV and 15 MeV , 1996 .

[14]  Michael Nicolaidis.  Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force? , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[15]  H. Kobayashi,et al.  A novel technique for mitigating neutron-induced multi -cell upset by means of back bias , 2008, 2008 IEEE International Reliability Physics Symposium.

[16]  G. Gasiot,et al.  Combined altitude and underground real-time SER characterization of CMOS technologies on the ASTEP-LSM platform , 2009, 2009 IEEE International Conference on IC Design and Technology.

[17]  M.D. Berg,et al.  Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM , 2009, IEEE Transactions on Nuclear Science.

[18]  A. N. Smirnov,et al.  Characterization of the ANITA Neutron Source for Accelerated SEE Testing at the Svedberg Laboratory , 2008, 2009 IEEE Radiation Effects Data Workshop.

[19]  E. Blackmore.  Development of a Large Area Neutron Beam for System Testing at TRIUMF , 2009, 2009 IEEE Radiation Effects Data Workshop.

[20]  Hasegawa Tatsuo,et al.  Analysis of Trap-State Density at Pentacene/Gate Insulator Interface Using In-Situ Field-Effect Thermally-Stimulated-Current Method , 2010 .

[21]  peixiong zhao,et al.  Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions , 2009, IEEE Transactions on Nuclear Science.

[22]  Shimbo Kenichi,et al.  Correlation of Mitigation of Soft-error Rate of Routers between Neutron Irradiation Test and Field Soft-error Data , 2009 .

[23]  Ming Zhang,et al.  On the Scalability of Redundancy based SER Mitigation Schemes , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[24]  Philippe Roche,et al.  Altitude SEE Test European Platform (ASTEP): Project Overview, First Results in CMOS 130nm and Perspectives , 2006 .

[25]  Shi-Jie Wen,et al.  Design for Soft Error Resiliency in Internet Core Routers , 2009, IEEE Transactions on Nuclear Science.

[26]  L. Borucki,et al.  Comparison of accelerated DRAM soft error rates measured at component and system level , 2008, 2008 IEEE International Reliability Physics Symposium.

[27]  S. S. Chung,et al.  Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling , 2006, IEEE Custom Integrated Circuits Conference 2006.

[28]  Jeita.  JEITA SER Testing Guideline , 2005 .