Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices
暂无分享,去创建一个
Gwan-Hyeob Koh | Dae-Won Ha | Kinam Kim | Dong-won Shin | Kinam Kim | G. Koh | D. Ha | C. Cho | Dong-won Shin | Taeyoung Chung | Tae-Young Chung | Chang-hyun Cho
[1] T. Park,et al. Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyond , 1998 .
[2] T. Nishimura,et al. Stress analysis of shallow trench isolation for 256 M DRAM and beyond , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[3] K. Yoshida,et al. Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[4] John Damiano,et al. Characterization and elimination of trench dislocations , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
[5] B.J. Park,et al. A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
[6] Kinam Kim,et al. DRAM technology perspective for gigabit era , 1998 .
[7] S.H. Hong,et al. Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[8] Umezawa,et al. Mechanical Stress Induced MOSFET Punch-through And Process Optimization For Deep Submicron TEOS-O/sub 3/ Filled STI Device , 1997, 1997 Symposium on VLSI Technology.
[9] S. Aur,et al. Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies , 1996, International Electron Devices Meeting. Technical Digest.
[10] H. Miura,et al. The impact of mechanical stress control on VLSI fabrication process , 1996, International Electron Devices Meeting. Technical Digest.
[11] Dae-Won Ha,et al. Shallow Trench Isolation for Enhancement of Data Retention Times in giga bit DRAM , 1996 .
[12] P. Fazan,et al. A highly manufacturable trench isolation process for deep submicron DRAMs , 1993, Proceedings of IEEE International Electron Devices Meeting.
[13] J. D. Mis,et al. Stress-induced dislocations in silicon integrated circuits , 1992, IBM J. Res. Dev..
[14] K. Ryoo,et al. Location Effects of Extended Defects on Electrical Properties of p+‐n Junction , 1989 .
[15] E. Weber,et al. Enhanced elimination of implantation damage upon exceeding the solid solubility , 1987 .
[16] J. Ziegler. Ion Implantation Science and Technology , 1984 .