TDCM: An IP watermarking algorithm based on two dimensional chaotic mapping

With the rapid development of VLSI (Very Large Scale Integration) circuit, IP (Intellectual Property) protection for reused technology is widely concerned. A watermarking scheme for IP protection is proposed on basis of a two dimensional chaotic mapping model (TDCM). The scheme utilizes a secure and controllable embedding model to compute the aggregation level of physical resource positions and the secure threshold of controllability. A two dimensional chaotic sequence is generated with the control of secure threshold. The first dimensional sequence is used to determine random watermark positions and the second dimensional sequence is to control watermark number in each position. Finally, the watermarks are inserted into corresponding places orderly. The experiments show that the proposed scheme has low resource overhead by comparing with other schemes. The resistance to attacks and robustness of the watermark are encouraging as well.

[1]  Sofiène Tahar,et al.  IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Jürgen Teich,et al.  Netlist-level IP protection by watermarking for LUT-based FPGAs , 2008, 2008 International Conference on Field-Programmable Technology.

[3]  Yvo Desmedt,et al.  Cryptanalysis of UCLA Watermarking Schemes for Intellectual Property Protection , 2002, Information Hiding.

[4]  Gang Qu,et al.  Publicly detectable watermarking for intellectual property authentication in VLSI design , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Sofiène Tahar,et al.  A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Amr T. Abdel-Hamid,et al.  A Survey on IP Watermarking Techniques , 2004, Des. Autom. Embed. Syst..

[7]  E. Castillo,et al.  Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection , 2008, 2008 4th Southern Conference on Programmable Logic.

[8]  Yu-Cheng Fan,et al.  Testing-Based Watermarking Techniques for Intellectual-Property Identification in SOC Design , 2008, IEEE Transactions on Instrumentation and Measurement.

[9]  Huanguo Zhang,et al.  Two-Dimension Chaotic-Multivariate Signature System , 2013 .

[10]  Fabien A. P. Petitcolas,et al.  Revised Papers from the 5th International Workshop on Information Hiding , 2002 .

[11]  Yongqiang Lyu,et al.  Efficient verification of IP watermarks in FPGA designs through lookup table content extracting , 2012, IEICE Electron. Express.

[12]  Miodrag Potkonjak,et al.  Signature hiding techniques for FPGA intellectual property protection , 1998, ICCAD '98.

[13]  Miodrag Potkonjak,et al.  Signature hiding techniques for FPGA intellectual property protection , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[14]  Miodrag Potkonjak,et al.  Effective iterative techniques for fingerprinting design IP , 1999, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Abhishek Basu,et al.  FPGA IMPLEMENTATION OF IP PROTECTION THROUGH VISUAL INFORMATION HIDING , 2011 .

[16]  Antonio García,et al.  IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Guanrong Chen,et al.  Generating Hyperchaos via State Feedback Control , 2005, Int. J. Bifurc. Chaos.

[18]  Jürgen Teich,et al.  Power Signature Watermarking of IP Cores for FPGAs , 2008, J. Signal Process. Syst..

[19]  Wei Liang,et al.  A Survey of Techniques for VLSI IP Protection , 2013 .

[20]  Bertrand Le Gal,et al.  Automatic low-cost IP watermarking technique based on output mark insertions , 2012, Des. Autom. Embed. Syst..

[21]  Daniel Ziener,et al.  Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs , 2010 .

[22]  Miodrag Potkonjak,et al.  Constraint-based watermarking techniques for design IP protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Zheng-Wei Shen,et al.  Blind watermarking algorithm based on henon chaos system and lifting scheme wavelet , 2009, 2009 International Conference on Wavelet Analysis and Pattern Recognition.

[24]  Guanrong Chen,et al.  Hyperchaos evolved from the generalized Lorenz equation , 2005, Int. J. Circuit Theory Appl..

[25]  Yao Zhao,et al.  Pinpoint authentication watermarking based on a chaotic system. , 2008, Forensic science international.

[26]  Xingming Sun,et al.  A Chaotic IP Watermarking in Physical Layout Level Based on FPGA , 2011 .

[27]  Sofiène Tahar,et al.  IP watermarking techniques: survey and comparison , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

[28]  Anastasios Tefas,et al.  Markov chaotic sequences for correlation based watermarking schemes , 2003 .

[29]  Arlindo L. Oliveira.  Techniques for the creation of digital watermarks in sequentialcircuit designs , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Qing-xin Zhu,et al.  A DCT Domain Color Watermarking Scheme Based on Chaos and Multilayer Arnold Transformation , 2009, 2009 International Conference on Networking and Digital Society.

[31]  Susmita Sur-Kolay,et al.  Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design , 2012, 2012 25th International Conference on VLSI Design.