A new highly-linear highly-sensitive differential voltage-to-time converter circuit in CMOS 65nm technology

Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital word. In this paper, a novel design of a differential VTC circuit is proposed which reports wider dynamic range and higher sensitivity than previously published VTC circuits in TSMC 65nm CMOS technology, with a supply voltage of 1.2V. This new VTC circuit operates with no sample and hold circuit for analog input frequencies up to 2.5 GHz with a linearity error of 3%.

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