PROVERIFIC: experiments in employing (PSL) standard assertions in theorem-proving-based verification

Using assertions with the design plays a central role in the design-for-verification (DFV) methodology, and hence, assertion-based design is becoming more and more widely used in industry. However, we believe that the advantages of assertions in formal verification have not been fully explored. In particular, there is little research that makes use of assertions in theorem proving. In this paper, we focus on this problem, and present our work on development of the semiautomated theorem-proving based verification system PROVERIFIC that makes use of existing design assertions. We have developed UFM, a unified modeling framework, where both the design and its assertions can be formally specified in predicate logic. Then, we defined generic predicate templates that capture the semantics of a subset of PSL assertions and a subset of Verilog within the syntax of UFM. During the verification exercise PROVERIFIC uses these templates to automatically extract formal models of a design (specified in Verilog) and its properties (specified in PSL) and translates them into higher-order logic predicates of the PVS theorem-proving system. Design verification can be further conducted by proving the correctness properties in PVS. We provide examples that demonstrate the effectiveness of our theorem proving approach for verification of designs with PSL assertions.