A Novel Static Dual Edge-Trigger Flip-flop for High-Frequency Low-Power Application

Abstract-In this paper, we propose a simple and novel Dual-edge-trigger flip-flop (DETFF). The design has a simple structure which consists of a XNOR pulse generator and a front end sampling circuit. All Simulations were performed at clock frequency of 800 MHz based on Chartered Semiconductor Manufacturing 0.18-mum CMOS technology. Comparison with some of the latest DETFFs shows that the proposed design can achieve the lowest power consumption and Power-delay-product (PDP). In addition, the proposed design has the least number of transistor and is of the least overall silicon area required.

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