A low power NoC router using the marching memory through type
暂无分享,去创建一个
Hideharu Amano | Masashi Watanabe | Tadao Nakamura | Yasunobu Nakase | Tsukasa Oishi | Toru Shimizu | Takahiro Kagami | Ryota Yasudo
[1] David Wentzlaff,et al. Energy characterization of a tiled architecture processor with on-chip networks , 2003, ISLPED '03.
[2] Michael Frumkin,et al. The OpenMP Implementation of NAS Parallel Benchmarks and its Performance , 2013 .
[3] Somayeh Sardashti,et al. The gem5 simulator , 2011, CARN.
[4] Sriram R. Vangal,et al. A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.