SPECTRAL TECHNIQUES FOR FAULT DETECTION1 IN COMBINATIONAL LOGIC

[1]  Mark G. Karpovsky.  Error detection for polynomial computations , 1979 .

[2]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[3]  Alfred K. Susskind,et al.  Testing by Verifying Walsh Coefficients , 1983, IEEE Transactions on Computers.

[4]  D. Michael Miller,et al.  Spectral Fault Signatures for Internally Unate Combinational Networks , 1983, IEEE Transactions on Computers.

[5]  Arnold L. Rosenberg,et al.  Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing , 1983, IEEE Transactions on Computers.

[6]  Jacob Savir,et al.  Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits , 1981, IEEE Transactions on Computers.

[7]  John P. Hayes,et al.  Transition Count Testing of Combinational Logic Circuits , 1976, IEEE Transactions on Computers.

[8]  Mark G. Karpovsky,et al.  Fourier Transform over Finite Groups for Error Detection and Error Correction in Computation Channels , 1979, Inf. Control..

[9]  John P. Hayes,et al.  CHECK SUM METHODS FOR TEST DATA COMPRESSION. , 1976 .

[10]  M. Karpovsky,et al.  Detection and location of errors by linear inequality checks , 1982 .

[11]  Mark G. Karpovsky.  Error Detection in Digital Devices and Computer Programs with the Aid of Linear Recurrent Equations Over Finite Commutative Groups , 1977, IEEE Transactions on Computers.

[12]  ADI TZIDON,et al.  A Practical Approach to Fault Detection in Combinational Networks , 1978, IEEE Transactions on Computers.

[13]  Sharad C. Seth,et al.  An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing , 1984, IEEE Trans. Computers.

[14]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[15]  James E. Smith.  Detection of Faults in Programmable Logic Arrays , 1979, IEEE Transactions on Computers.

[16]  Mark G. Karpovsky,et al.  Linear Checking Equations and Error-Correcting Capability for Computation Channels , 1977, IFIP Congress.

[17]  George Markowsky,et al.  The Weighted Syndrome Sums Approach to VLSI Testing , 1981, IEEE Transactions on Computers.

[18]  George Markowsky,et al.  Syndrome-Testability Can be Achieved by Circuit Modification , 1981, IEEE Transactions on Computers.

[19]  D. M. Miller,et al.  Syndrome-testable internally unate combinational networks , 1983 .

[20]  D. Michael Miller,et al.  Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks , 1984, IEEE Transactions on Computers.

[21]  Jon C. Muzio.  Composite Spectra and the Analysis of Switching Circuits , 1980, IEEE Transactions on Computers.

[22]  Jacob Savir,et al.  Syndrome-Testable Design of Combinational Circuits , 1980, IEEE Transactions on Computers.