New Leakage Reduction Techniques for FinFET Technology with Its Application

This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32nm technology node at 25∘C and 110∘C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25∘C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% ...

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