Applying March Tests to K-Way Set-Associative Cache Memories

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system test. The application of test algorithms for SRAM memories to cache memories thus requires opportune transformations. In this paper we present a procedure to adapt traditional march tests to testing the data and the directory array of k-way set-associative cache memories with LRU replacement. The basic idea is to translate each march test operation into an equivalent sequence of cache operations able to reproduce the desired marching sequence into the data and the directory array of the cache.

[1]  Yervant Zoriaii.  Effective March Algorithms for Testing Single-Order Addressed Memories , 1993 .

[2]  Wen-Ben Jone,et al.  Fault Modeling and Detection for Drowsy SRAM Caches , 2006, 2006 IEEE International Test Conference.

[3]  Sandeep K. Gupta,et al.  A methodology for transforming memory tests for in-system testing of direct mapped cache tags , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[4]  S. Hamdioui,et al.  Converting March tests for bit-oriented memories into tests for word-oriented memories , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[5]  Dileep Bhandarkar,et al.  Performance characterization of the Pentium Pro processor , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

[6]  A.J. van de Goor,et al.  Functional testing of modern microprocessors , 1992, [1992] Proceedings The European Conference on Design Automation.

[7]  Janusz Sosnowski.  In-system testing of cache memories , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[8]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[9]  Robert F. Molyneaux,et al.  Random self-test method applications on PowerPC/sup TM/ microprocessor caches , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[10]  Tariq Jamil,et al.  Cache memories , 2000 .