Se1 f-C heckin g Architectures for Fast Har tley Trans form

For many real-time and scientific applications, it is desirable to perform signal and image processing algorithms by means of special hardware in very high speed. With the advent of VLSI technology, large collections of processing elements can be used to achieve high-speed computations. In such designs, fault detection is required to ensure the validity of the results. The Fast Mey Transform (FHT) serves for all the uses such as spectral analysis and digital convolution to which the FFT is currently applied. It can be applied as a more convenient way of calculating the FFT without the need to work on complex numbers. In this paper we present self-checking amy architectures for the radix-2 FHT transform and for Fermat number tnnsform (F”ed HNtley transform. The results show that it is possible to design algorithm-based error detection schemes for both the direct (FFT like) FHT and the FNT-based FHT with reasonable hardware and time overheads.