Implementation of UART with Parallel CRC Based on FPGA

In data communication based on universal asynchronous receiver and transmitter(UART),cyclic redundancy cod,or CRC,is usually used.The familiar CRC circuits are serial,this kind circuit takes one cycle per bit.Parallel arithmetic based of look-up table or converted input matrix requires mounts of memories to storage the residue data.Take up a lot of hordware resources.The method here utilizes the logic relationship between input and residues are brought to UART controller.It was implemented on field programmable gate array(FPGA)from Xilinx.It takes only eighth cycles,reduces frequency of verification,improves the efficiency of communication,guarantees the reliability of communication.