Power Loop Busbars Design and Experimental Validation of 1 kV, 5 kA Solid-State Circuit Breaker Using Parallel Connected RB-IGCTs

This article investigates the design of a 1 kV, 5 kA solid-state circuit breaker by using parallel connection of reverse blocking IGCTs (RB-IGCT). The presented breaker topology is based on the parallel connection of low conduction loss RB-IGCTs which delivers efficiency as high as 99.9%. The focus of this article is on the power loop design and experimental validation of parallel connection of two and three RB-IGCTs with emphasis on current sharing during dynamic events such as short-circuits. A 3-D CAD-based design of power loop busbars was verified by several simulation test cases to represent dynamic current sharing under variations in RB-IGCT package impedances. An optimized busbar design approach and its tradeoffs are also discussed with simulation verification. The experimental results confirm that the parallel topology is able to perform current interruption during overload and short-circuit situations up to 10 kA for two devices in parallel and up to 14 kA for three devices in parallel - with current deviation from the mean as little as 6%.