A Comparison of Two Architectural Power Models

Reducing power, on both a per cycle basis and as the total energy used over the lifetime of an application, has become more important as small and embedded devices become increasingly available. A variety of techniques are available to reduce power, but it is difficult to quantify the benefits of these techniques early in the system design phase when processor architecture is being defined. Accurate tools that allow for exploration of the design space during this phase are crucial. This paper describes our experience with two such tools, the Cai-Lim power model and Wattch, which have been made available to the computer architecture community over the past year. We focus on how the models are constructed, the granularity of activity revealed by the models, the ability to understand why particular power results are obtained and the accuracy of the models. We raise concerns about detailed simulations where the power model, the simulator model and the desired architecture to be simulated differ and the validity of data obtained in such situations.