Weighted bit-set encodings for redundant digit sets: theory and applications

This paper aims to fill the gap between theoretical studies of redundant number representation dealing with digit-level algorithms, without considering circuit-level details or impact of digit-set encodings, and implementation-oriented studies that typically focus on one particular digit-set encoding. We recognize that radices of practical interest are powers of two, giving each high-radix digit a weight that is a power of two. Furthermore, digit sets are typically encoded in such a way that each bit of the encoded form has a power-of-2 weight within the corresponding position. These observations lead us to define the class of weighted bit-set (WBS) encodings for redundant number systems and study the general properties of this class of representations. While by no means completely general, the class of WBS encodings includes virtually every implementation of redundant arithmetic that we have encountered, including those based on hybrid redundancy. We derive general conditions for a WBS encoding to be viable or efficient and describe how arithmetic operations can be performed on redundant numbers of this type using standard arithmetic components such as full/half-adders and multiplexers.

[1]  M.D. Ercegovac,et al.  A multiplier with redundant operands , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[2]  Behrooz Parhami,et al.  Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations , 1990, IEEE Trans. Computers.

[3]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[4]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[5]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[6]  Dhananjay S. Phatak,et al.  Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains , 1994, IEEE Trans. Computers.

[7]  B. Parhami,et al.  A class of stored-transfer representations for redundant number systems , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[8]  Behrooz Pamami,et al.  Generalized Signed-Digit Number Systems : A Unifying Framework for Redundant Number Representations , 1990 .

[9]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[10]  Dhananjay S. Phatak,et al.  Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations , 2001, IEEE Trans. Computers.

[11]  G Jaberipour,et al.  High Radix Signed Digit Number Systems: Representation Paradigms , 2003 .