Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach

Linear computations form an important type of computation that is widely used in DSP and communications. We introduce two approaches for power minimization in linear computations using transformations. First we show how unfolding combined with the procedure for maximally fast implementation of linear computations reduces power in single processor and multiprocessor implementations by factors 2.2 and 8 respectively. To accomplish this we exploit a newly identified property of unfolding whereby as a linear system is unfolded, the number of operations per sample at first decreases to reach a minimum and then begins to rise. For the custom ASIC implementation even higher improvements are achievable using the second transformational approach, which builds upon the unfolding based strategy of the first approach. We developed a method that combines the multiple constant multiplication technique with the generalized Horner's scheme and unfolding in such a way that power is minimized.

[1]  Miodrag Potkonjak,et al.  Transforming linear systems for joint latency and throughput optimization , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[2]  Massoud Pedram,et al.  Power conscious CAD tools and methodologies: a perspective , 1995, Proc. IEEE.

[3]  Miodrag Potkonjak,et al.  An Approach For Power Minimization Using Transformations , 1992, Workshop on VLSI Signal Processing.

[4]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[5]  Donald Ervin Knuth,et al.  The Art of Computer Programming, Volume II: Seminumerical Algorithms , 1970 .

[6]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[7]  MalikSharad,et al.  Power analysis of embedded software , 1994 .

[8]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[9]  Mani B. Srivastava,et al.  Energy efficient programmable computation , 1994, Proceedings of 7th International Conference on VLSI Design.

[10]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, ICCAD.

[11]  Dan Zuras,et al.  Integer multiplication and division on the HP precision architecture , 1987, IEEE Trans. Computers.

[12]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[13]  Stephen A. Dyer,et al.  Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..

[14]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[15]  Herman H. Goldstine,et al.  Preliminary discussion of the logical design of an electronic computing instrument (1946) , 1989 .

[16]  Robert L. Bernstein.  Multiplication by integer constants , 1986, Softw. Pract. Exp..

[17]  Dan Zuras,et al.  Integer multiplication and division on the HP precision architecture , 1987 .

[18]  Miodrag Potkonjak,et al.  Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching , 1994, 31st Design Automation Conference.

[19]  Miodrag Potkonjak,et al.  Maximally fast and arbitrarily fast implementation of linear computations , 1992, ICCAD '92.

[20]  Hugo De Man,et al.  Global Communication and Memory Optimizing Transformations for Low Power Systems , 1994 .

[21]  Kaushik Roy,et al.  Circuit activity based logic synthesis for low power reliable operations , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Miodrag Potkonjak,et al.  Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

[23]  Lance A. Glasser,et al.  Delay and Power Optimization in VLSI Circuits , 1984, 21st Design Automation Conference Proceedings.

[24]  Giovanni De Micheli,et al.  High Level Synthesis of ASlCs un - der Timing and Synchronization Constraints , 1992 .

[25]  Donald E. Thomas,et al.  Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..