Design of an integrated tunable differential negative resistance in UMC 0.18 μm

This paper presents a CMOS floating tunable differential resistance, which has the property of being positive with respect to common-mode signals while being negative for differential signals. The designed circuit is simulated in UMC 180nm CMOS process: simulations show that the negative differential resistance can be varied in a broad range, from 23.5k? to 3.8M?.

[1]  Hideki Asai,et al.  A low voltage floating resistor having positive and negative resistance values , 2002, Asia-Pacific Conference on Circuits and Systems.

[2]  Sezai Alper TEK,et al.  Novel Low Voltage CMOS Current Controlled Floating Resistor Using Differential Pair , 2013 .

[3]  Kwang-Jow Gan,et al.  Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process , 2011, Microelectron. J..

[4]  Li Wang,et al.  An adjustable CMOS floating resistor , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[5]  P.B. Griffin,et al.  Negative Differential Resistance Circuit Design and Memory Applications , 2009, IEEE Transactions on Electron Devices.

[6]  Raphael Tsu,et al.  Superlattice and negative differential conductivity in semiconductors , 1970 .

[7]  Kyung Rok Kim,et al.  Novel design of multiple negative-differential resistance (NDR) device in a 32nm CMOS technology using TCAD , 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

[8]  W. Jaikla,et al.  Floating Positive/Negative Resistance Simulators Employing Single Dual-output OTA , 2006, 2006 International Symposium on Communications and Information Technologies.

[9]  Juan Núñez,et al.  Novel pipeline architectures based on Negative Differential Resistance devices , 2013, Microelectron. J..

[10]  Dong-Shong Liang,et al.  Investigation of MOS-NDR Voltage Controlled Ring Oscillator Fabricated by CMOS Process , 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

[11]  Yi Wei,et al.  Design of nanopipelined adder based on resonant tunneling diode , 2012, Microelectron. J..

[12]  William Song,et al.  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[13]  Maria J. Avedillo,et al.  Using multi-threshold threshold gates in RTD-based logic design: A case study , 2005, Microelectron. J..

[14]  Montree Kumngern CMOS Tunable Positive/Negative Floating Resistor Using OTAs , 2012, 2012 Fourth International Conference on Computational Intelligence, Communication Systems and Networks.

[15]  Mohammad S. Hashmi,et al.  A digitally controlled floating resistor using CMOS translinear cells , 2014, 2014 Recent Advances in Engineering and Computational Sciences (RAECS).

[16]  Hideki Asai,et al.  A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).