Improving power efficiency in stream processors through dynamic cluster reconfiguration
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[1] William J. Dally,et al. Exploring the VLSI scalability of stream processors , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..
[2] Joseph R. Cavallaro,et al. Design space exploration for real-time embedded stream processors , 2004, IEEE Micro.
[3] W. Dally,et al. Efficient conditional operations for data-parallel architectures , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[4] S. Wicker. Error Control Systems for Digital Communication and Storage , 1994 .
[5] Jeffrey Posluns,et al. The Wireless Challenge , 2002 .
[6] William J. Dally,et al. The VLSI implementation and evaluation of area-and energy-efficient streaming media processors , 2003 .
[7] Lawrence T. Clark,et al. An embedded 32-b microprocessor core for low-power and high-performance applications , 2001 .
[8] William J. Dally,et al. Register organization for media processing , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).
[9] Srikrishna Bhashyam,et al. Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers , 2002, IEEE Trans. Wirel. Commun..
[10] William J. Dally,et al. Programmable Stream Processors , 2003, Computer.