A SAW-less 0.5–2.5 GHz receiver front-end with 80 dB 3rd order harmonic rejection ratio

This paper presents a 65 nm SAW-less receiver front-end. Using 3-phase clocks for impedance translation, an RF filter with 3rd order harmonic rejection is obtained. Employing this filter as the front-end's input matching network and a two-stage low noise amplifier's load, a 3rd order RF filter is realized. In addition, by using 3-phase 1/3-duty-cycle LO, a 3rd order harmonic rejection mixer is realized. The mixer's harmonic rejection ratio is less sensitive to gain and phase error compared to conventional 8-phase mixers, since the 3-path's gain ratio is 1:2:1. These two techniques enhance 3rd order harmonic rejection ratio to 80 dB in case of 6% duty-cycle error, 2% gain error and 0.5° phase error. The front-end achieves a noise figure of 3-6 dB from 0.5 GHz to 2.5 GHz, consumes 21-33 mW power from a 1.2 V voltage supply and occupies an area of 0.35 mm2.

[1]  Eric A. M. Klumperink,et al.  Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification , 2011, IEEE Journal of Solid-State Circuits.

[2]  L. Franks,et al.  Solid-state sampled-data bandpass filters , 1960 .

[3]  Li Lin,et al.  A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[4]  Ahmad Mirzaei,et al.  A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications , 2012, IEEE Journal of Solid-State Circuits.

[5]  N. A. Moseley,et al.  Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference , 2009, IEEE Journal of Solid-State Circuits.

[6]  Stefan Back Andersson,et al.  Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Peter R. Kinget,et al.  A 0.5GHz–1.5GHz order scalable harmonic rejection mixer , 2013, 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[8]  Nobuyuki Itoh,et al.  A 6-phase harmonic rejection down-converter with digital assist , 2010, 2010 Symposium on VLSI Circuits.

[9]  Ahmad Mirzaei,et al.  Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  H. Darabi,et al.  A 65nm CMOS quad-band SAW-less receiver for GSM/GPRS/EDGE , 2010, 2010 Symposium on VLSI Circuits.