Enhanced Circuit Densities in Epitaxially Defined FinFETs (EDFinFETs) over FinFETs

FinFET technology is prone to suffer from Line Edge Roughness (LER) based VT variation with scaling. To address this, we proposed an Epitaxially Defined (ED) FinFET (EDFinFET) as an alternate to FinFET architecture for 10 nm node and beyond. We showed by statistical simulations that EDFinFET reduces LER based VT variability by 90% and overall variability by 59%. However, EDFinFET consists of wider fins as the fin widths are not constrained by electrostatics and variability (cf. FinFETs have fin width ~ LG/3 where LG is gate-length). This indicates that EDFinFET based circuits may be less dense. In this study we show that wide fins enable taller fin heights. The ability to engineer multiple STI levels on tall fins enables different transistor widths (i.e. various W/Ls e.g. 1-10) in a single fin. This capability ensures that even though individual EDFinFET devices have ~2x larger footprints than FinFETs, EDFinFET may produce equal or higher circuit density for basic building blocks like inverters or NAND gates for W/Ls of 2 and higher.

[1]  R. Engelbrecht,et al.  DIGEST of TECHNICAL PAPERS , 1959 .

[2]  Andrew R. Brown,et al.  Statistical variability and reliability in nanoscale FinFETs , 2011, 2011 International Electron Devices Meeting.

[3]  K. Yahashi,et al.  Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[4]  C. Hu,et al.  Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights , 2012, IEEE Transactions on Electron Devices.

[5]  Torsten Lehmann,et al.  Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology , 2011, IEEE Journal of Solid-State Circuits.

[6]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[7]  Ying Zhang,et al.  Extension and source/drain design for high-performance FinFET devices , 2003 .

[8]  S. Keller,et al.  Formation of sub-10 nm width InGaAs finFETs of 200 nm height by atomic layer epitaxy , 2013, 71st Device Research Conference.

[9]  H. Ishiuchi,et al.  Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[10]  S. Lodha,et al.  Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT , 2012, 70th Device Research Conference.

[11]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[12]  Krishna Duvvada.  HIGH SPEED DIGITAL CMOS INPUT BUFFER DESIGN , 2006 .

[13]  Kinam Kim,et al.  Technology for sub-50nm DRAM and NAND flash manufacturing , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[15]  Udayan Ganguly,et al.  Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology , 2014, IEEE Transactions on Electron Devices.

[16]  Krishna Parat,et al.  25nm 64Gb MLC NAND technology and scaling challenges invited paper , 2010, 2010 International Electron Devices Meeting.