Using Block SelectRAM Memories as Serializers or Deserializers

This application note describes how block memories efficiently can implement a serializer or a deserializer function or both with or without pattern matching capabilities in the Virtex™-II, Virtex-II Pro™, and Spartan™-3 architectures. The used method can deserialize or serialize with or without data storage. The resulting implementation can be used in either dual-port or single-port mode, with full functionality at the maximum speed of the Block SelectRAM. Introduction Since the original Virtex device was introduced, users have had access to block memories in the Xilinx architecture. These 4 Kbit blocks in the Virtex, VirtexE, and Spartan-II devices were increased in size to 18 Kbit blocks in the Virtex-II, Virtex-II Pro, and Spartan-3 devices. These blocks are fully synchronous, true dual-port structures. That is, the user can read from or write to each port independently (with the exception of simultaneous reads and writes to the same address). In addition, each port has a separate clock, and the data widths for each port are independently programmable. Figure 1 shows a block diagram of the dual-port RAM blocks. Today's high-speed communications between chips, boards, or systems typically are done serially. Xilinx has implemented dedicated Multi Gigabit Transceiver (MGT) devices in each Virtex-II Pro FPGA. Alternatively, other FPGAs can use externally placed MGTs for high-speed serial communication designs. Often, however, serial communication at lower speeds is needed. Then any device with Block SelectRAM can implement serializers/deserializers using the ideas described in this application note. Application Note: Virtex-II, Virtex-II Pro, Spartan-3 Families