论文信息 - Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs

Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs

This paper describes novel offset, gain-error, and clock-skew minimization techniques for required channel matching of multi-channel ADCs. The proposed adaptive closed-loop offset sampling enhances the operating speed of a parallel pipeline ADC with removed channel offsets. The 10b 200MS/s 0.13/spl mu/m CMOS ADC achieves the SNDR of 55dB for a 21 MHz sinusoidal input at 200MS/S without any other offset calibration. Based on the prototype ADC evaluation, a clock-skew reduction scheme is proposed to improve further the dynamic gain mismatch between channels of parallel ADCs.

Seung-Hoon Lee | Seung-Chul Lee | Jong-Kee Kwon | Jongdae Kim | Gyu-Hyun Kim

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