A synchronous wrapper for high-speed heterogeneous systems on FPGAs

Taking advantage of synchronous and asynchronous paradigms, a new style of design, called Globally Synchronous Locally Asynchronous (GSLA), has achieved very interesting results. In this paper, we propose a synchronous wrapper that allows the communication of “synchronous to asynchronous to synchronous” modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is interesting for Field-Programmable Gate Array (FPGA) platforms because it facilitates the design of Application Specific Integrated Circuits (ASIC). Through two case studies, the “differential equation solver” and the “FIR Filter”, we show that the proposed synchronous wrapper presents a reduction of up to 27% in the processing time and an increase of up to 747% in the global clock rate when compared with the synchronous design.

[1]  Steven M. Nowick,et al.  The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Chris J. Myers,et al.  Interlocked synchronous pipelines , 2004 .

[4]  Kiyoshi Oguri,et al.  Asynchronous Circuit Design , 2001 .

[5]  Peter Y. K. Cheung,et al.  Asynchronous wrapper for heterogeneous systems , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[6]  María José Moure,et al.  Features, Design Tools, and Application Domains of FPGAs , 2007, IEEE Transactions on Industrial Electronics.

[7]  Luciano Lavagno,et al.  Coping with the variability of combinational logic delays , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[8]  Guy Lemieux,et al.  A Survey and Taxonomy of GALS Design Styles , 2007, IEEE Design & Test of Computers.

[9]  Kwen-Siong Chong,et al.  Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips , 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

[10]  Chris J. Myers,et al.  Interfacing synchronous and asynchronous modules within a high-speed pipeline , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Alexander V. Rylyakov,et al.  An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz , 2002, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  D. Dill,et al.  Automatic Synthesis of Extended Burst-Mode Circuits : Part II ( Automatic Synthesis ) , 1996 .

[13]  Osman Hasan,et al.  Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[14]  Peter W. Cook,et al.  Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz , 2003 .

[15]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[16]  C. Rajasekaran,et al.  Design of high performance system-on-chips using Field Programmable Gate Arrays (FPGA) , 2014, 2014 International Conference on Communication and Signal Processing.

[17]  Kenneth Y. Yun,et al.  Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations) , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Tiago Curtinhas,et al.  Synthesis of locally-clocked asynchronous systems with bundled-data implementation on FPGAs , 2014, 2014 IX Southern Conference on Programmable Logic (SPL).

[19]  Vaughn Betz,et al.  Quantifying the cost and benefit of latency insensitive communication on FPGAs , 2014, FPGA.

[20]  Peter W. Cook,et al.  to synchronously to asynchronous interface of synchronism , 2002 .

[21]  Duarte L. Oliveira,et al.  Using FPGAs to implement asynchronous pipelines , 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

[22]  D. L. Oliveira,et al.  Design of Asynchronous Digital Systems using Two-Phase Bundled-Data Protocol , 2012, 2012 VI Andean Region International Conference.

[23]  Ran Ginosar,et al.  An asynchronous instruction length decoder , 2001, IEEE J. Solid State Circuits.