A high-performance VLSI architecture for MAPS criterion motion estimation

In this paper, a novel block-matching criterion called partitioned mean absolute error of projective sum (PMAPS) is proposed to reduce the computational complexity of block-based motion estimation. With approximate prediction quality and compression efficiency as the mean absolute difference (MAD), the PMAPS can save about 50% computational load of MAD by the fast algorithm presented. Based on its simple and regular properties, a versatile 1-D array architecture and its VLSI implementation are developed with the characteristics of 100% hardware utilization, simple control, and flexible and modular structures.