This paper describes the design and fabrication of 4H-SiC, n-channel Power MOSFETs. For the first time, we have achieved 350 V, 10 A (V/sub F/=4.4 V) devices with an active area of 0.105 cm/sup 2/ (3.3 mm /spl times/3.3 mm). This represents a specific on-resistance of 43 m/spl Omega//spl middot/cm/sup 2/ for a cell pitch of 25 /spl mu/m (160,000 cells/cm/sup 2/). We have also achieved R/sub on,sp/=23 m/spl Omega//spl middot/cm/sup 2/ on smaller cells with a cell pitch of 16 /spl mu/m (390,000 cells/cm/sup 2/). An important issue in 4H-SiC MOSFETs is extremely low effective channel mobility (/spl mu//sub neff/) in the implanted p-well regions. It is shown that Al-implanted p-wells require at least 1600/spl deg/C activation anneal to achieve reasonable bulk hole mobility. Annealing at high temperatures causes surface roughness which degrades /spl mu//sub neff/ compared to low power MOSFETs made on a p-epilayer. NO annealing of the gate oxide and a buried channel structure are used for increasing /spl mu//sub neff/. A Buried channel (BC) structure with 1.7/spl times/10/sup 12/ cm/sup -2/ charge in the channel showed a high /spl mu//sub neff/ (195 cm/sup 2//V/spl middot/s) utilizing bulk buried channel, but resulted in a normally-on device. However, it is shown that by controlling the charge in the BC layer, a normally-off device with a high /spl mu//sub neff/ can be produced.
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